Frontiers in Analog CAD
February 14-15, 2013
David Brower Center, Berkeley, CA
Even in pre-dominantly digital systems, modern chips integrate onto a single die a significant amount of analog content, including high speed IOs, memory interfaces, thermal sensors, and a multitude of PLLs. Despite the vast majority of the transistors being dedicated to the digital circuitry, the limited number of analog transistors often consume just as many design and verification resources. Using current methodologies, even well- understood analog circuits require nearly as much effort to modify and/or port to a new process as the initial design. Even when an analog circuit can be re-used, validating its performance within the new system – especially if the circuit is controlled through a digital loop – is often the long pole in the overall flow. The reasons for this situation are both technical and sociological; inherent differences in the behaviors of digital vs. analog systems make analog design and validation much more resistant to automation. Similarly, the cultural distance between the EDA software developers and analog designers is much larger than the distance between them and digital designers.
The goal of this workshop is to bring together technologists and researchers from analog design as well as CAD tool development to foster collaboration and exchange of ideas as well as to spur further research into the intersection of these domains. In this spirit, the workshop will be held near the IEEE International Solid-State Circuits Conference, making it convenient for the design community to participate in what has traditionally been a CAD-centric workshop.
Registration and Accomodations
Registration and accomodation information is available at this link.
Call for Abstracts
Abstract Submission: Abstracts are submitted via email@example.com. Abstracts should be in PDF form, up to 2 pages in length with 1-inch margins and at least 10-point font size, and may contain up to two figures. Abstracts should list the full names, affiliations, and contact information of all authors, and the submission should indicate whether the abstract will be presented as a poster, orally, or both. Abstracts will be reviewed by the Program Committee. Those that are selected for oral and poster presentations will be distributed to workshop participants and posted on the workshop website.
- Submission deadline extended to Nov 12, 2012 by midnight Pacific time.
- Dec 20, 2012: Decision communicated to the authors
- The workshop will take place at David Brower Center in downtown Berkeley, right next to the UC Berkeley campus.
Topics of Interest
- Methodologies to enable increased levels of automation in analog design and verification
- Automatic generation of high-quality analog and mixed-signal layout
- Modeling approaches for analog circuits at varying levels of abstraction
- Verification of continuous models using hybrid system techniques
- Model checking and theorem proving methods
- Fast functional and behavioral simulation of AMS circuits
- Elad Alon, University of California, Berkeley, USA
- Thao Dang, CNRS/VERIMAG, France
- Chandramouli Kashyap, Intel Corporation, USA
- Emrah Acar, IBM
- Prabal Bhttacharya, Cadence
- Helmut Graeb, technical univ. of Munich
- Mark Greenstreet, University of British Columbia
- Christoph Grimm, TU Wien, Austria
- Lars Hedrich, Johann Wolfgang Goethe-Universität
- Mark Horowitz, Stanford University
- Kevin Jones, City University London
- Jeaha Kim, Seoul National University
- Peng Li, Texas A&M
- Xin Li, CMU
- Scott Little, Intel
- Oded Maler, Verimag
- Chris Myers, University of Utah
- Sunderarajan S. Mohan, Synopsys
- Rob Rutenbar, University of Illinois at Urbana-Champaign
This workshop is partly a successor of the FAC (formal
verification of analog circuits) workshop held in 2005, 2008, 2009, 2011.
Information about past workshops can be found at: