Frontiers in Analog CAD

Co-located with the International Solid-State Circuits Conference ISSCC

February 14-15, 2013

David Brower Center, Berkeley, CA

Even in pre-dominantly digital systems, modern chips integrate onto a single die a significant amount of analog content, including high speed IOs, memory interfaces, thermal sensors, and a multitude of PLLs. Despite the vast majority of the transistors being dedicated to the digital circuitry, the limited number of analog transistors often consume just as many design and verification resources. Using current methodologies, even well- understood analog circuits require nearly as much effort to modify and/or port to a new process as the initial design. Even when an analog circuit can be re-used, validating its performance within the new system – especially if the circuit is controlled through a digital loop – is often the long pole in the overall flow. The reasons for this situation are both technical and sociological; inherent differences in the behaviors of digital vs. analog systems make analog design and validation much more resistant to automation. Similarly, the cultural distance between the EDA software developers and analog designers is much larger than the distance between them and digital designers.

The goal of this workshop is to bring together technologists and researchers from analog design as well as CAD tool development to foster collaboration and exchange of ideas as well as to spur further research into the intersection of these domains. In this spirit, the workshop will be held near the IEEE International Solid-State Circuits Conference, making it convenient for the design community to participate in what has traditionally been a CAD-centric workshop.

Workshop Program

Technical Program

Registration and Accomodations

Registration and accomodation information is available at this link.

Call for Abstracts

Abstract Submission: Abstracts are submitted via Abstracts should be in PDF form, up to 2 pages in length with 1-inch margins and at least 10-point font size, and may contain up to two figures. Abstracts should list the full names, affiliations, and contact information of all authors, and the submission should indicate whether the abstract will be presented as a poster, orally, or both. Abstracts will be reviewed by the Program Committee. Those that are selected for oral and poster presentations will be distributed to workshop participants and posted on the workshop website.

Important Dates:

Topics of Interest

Program Chairs

Program Committee

Workshop History

This workshop is partly a successor of the FAC (formal verification of analog circuits) workshop held in 2005, 2008, 2009, 2011. Information about past workshops can be found at:

Steering Committee