Technical Program

Thursday - 14 Feb

8:00 - 8:20 Welcome

8:20 - 10:30 Session 1:

8:20 - ­9:20 Invited talk/tutorial: “High-­‐Speed I/O System and Circuit Design: Reality versus Vision” by Bryan Casper, Intel corp.

9:20 -­ 9:40 “ASDeX-­‐driven Analog Circuit Verification” by Mingyu Ma, Lars Hedrich and Sebastian Steinhorst slides

9:40 - ­10:00 “AMS Circuit Generation, It’s in the BAG”, by John Crossley, Alberto Puggelli, Hanh-­‐Phuc Le, Bonjern Yang, Rachel Nancollas, Lingkai Kong, Nicholas Sutardja, Eun Ji An and Elad Alon

10:00 - ­10:30 Panel discussion on session topic/Q&A with speakers

10:30 - 10:45 BREAK

10:45 - 1:00 Session 2:

10:45 - 11:30 Invited talk: “Enabling Analog Automation: an Industry Perspective” by Vinod Kariat, Cadence

11:30-­‐11:50 “Markov Network Based Equivalence Checking in Mixed-­‐Signal Systems” by Sangho Youn and Jaeha Kim slides

11:50 - ­12:10 “Analog Fault Sensitivity Analaysis (FSA) In Spectre” by Don O’riordan, Victor Zhuk, Ilya Yusim and Bratislav Tasic slides

12:10 - 12:30 “Strength-­‐Based Analog/Digital Interface For AMS Simulation” by Junwei Hou slides

12:30 - 1:00 Panel discussion on session topic/Q&A with speakers

1:00 - 2:30 LUNCH

2:30 - 4:45 Session 3:

2:30 ‐ 3:15 Invited talk: “Faith, Trust, and Pixie Dust: Achieving Trustworthy Industrial-Scale Variation-Aware AMS & Memory Verification” by Trent McConaghy, Solido Design

3:15 - 3:35 “Verification of Mixed-­‐Signal Systems with Range Based Signal Representations” by Michael Kargel, Markus Olbrich and Erich Barke slides

3:35 - 3:55 “Empirical Flowpipe Constructions for Analog Circuits” by Yan Zhang, Xin Chen, Sriram Sankaranarayanan and Erika Abraham slides

3:55 - 4:15 “Using Model-­‐Predictive Control and Linear Programming to Bridge Simulation and Formal Verification” by Shabab M. Hossain and Mark R. Greenstreet slides

4:15 - 4:45 Panel discussion on session topic/Q&A with speakers

4:45 - 5:00 BREAK


Topic: Will system designers without analog expertise ever be able to successfully build complex SoCs with substantial analog content?

Greg Taylor, Intel
Joel Philips, Cadence
Martin Vlach, Mentor Graphics slides
Arthur Redfern (TI)
Jaeha Kim, Seoul National University


Friday - 15 Feb

8:30 -­ 10:45 Session 1:

8:30 - ­9:30 Invited talk/tutorialon Hybrid Systems by Ian Mitchell

9:30 - 9:50 “Rapidly-Exploring Random Forests: Algorithms and Applications in Verification of Analog Circuits” by Seyed Nematollah Ahmadyan and Shobha Vasudevan

9:50 - 10:10 “Combining reachability and discrepancy information to improve test coverage” by Thao Dang and Noa Shalev slides

10:10 - 10:30 “Reachability Analysis for AMS Verification using Hybrid Support Function and SMT-based Method” by Honghuang Lin and Peposterng Li slides

10:30 - 11:00 Panel discussion on session topic/Q&A with speakers

11:00 - 12:30 POSTER SESSION

"High-Order Full-Load Operating Point Modeling for Design Synthesis of PFM Flyback Switching DC-DC Voltage Converters" by Darryl Phillips and Talal Al-Attar poster

"Symmetry Computation for Hierarchical Analog Designs" by Michael Eick, Devanathan Sridharan and Helmut Graeb poster

"Generation of Piecewise-Linear Semiconductor Models for Accelerated Mixed-Signal Simulation" by Stefan Hoelldampf, Hyun-Sek Lukas Lee, Markus Olbrich and Erich Barke poster

"Assertion-based Verification of Phase-Locked Look Circuit with Affine Arithmetic" by Carna Radojicic, Christoph Grimm, Florian Schufer and Michael Rathmair poster

"Investigations of Analog Behavioral Model Abstractions" by Martin Vlach poster

"Formal Verification of Continuous Models of Analog Circuits" by Syeda Hira Taqdees, and Osman Hasan poster

12:30 - 1:30 LUNCH

1:30 ‐ 3:00 Session 2:

1:30 - 1:50 “Frequency Domain Properties Verification of Analog Circuits using SMT” by Haz Ul Asad and Kevin.D Jones slides

1:50 - 2:10 “A New Assertion Property Language for Analog/Mixed-­‐Signal Circuits” by Dhanashree Kulkarni, Andrew Fisher and Chris J. Myers slides

2:10 ‐ 2:30 “Time-­‐Frequency Logic” by Alexandre Donze and Oded Maler

2:30 - 3:00 Panel discussion on session topic/Q&A with speakers

3:00 - 3:15 BREAK

3:15 ‐ 4:00 PANEL: Future directions for FAC

4:00 Concluding the workshop